A significant trend throughout integrated circuit (IC) development is the downsizing of IC components. These integration improvements are two-dimensional (2D) in nature where the ICs are integrated on a surface of a semiconductor wafer. Although dramatic improvement in lithography has enabled greater results in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. Also, when more devices are put into one chip, more complex designs and more costs are required.
In an attempt to further increased circuit density, three-dimension (3D) ICs have been developed. For example, two dies are boned together; and electrical connections are constructed between each die. The stacked dies are then bonded to a carrier substrate by using wire bonds and/or conductive pads. In another example, a chip on chip-on-substrate (Co(CoS)) or chip-on wafer on substrate (CoWoS) technique is developed.